1. Field of the Invention
The present invention relates to an electrostatic discharge (ESD) protection circuit, and more particularly, to an ESD protection circuit in a drive integrated circuit (IC) chip of a display supporting a dot inversion scheme.
2. Description of Related Art
In general, electrostatic discharge (ESD) protection circuits are provided between pads, referred to as ‘input/output pads’ hereafter, to which internal circuits of a semiconductor device and external input/output pins are connected, to prevent products from being broken down and deteriorated due to static electricity.
When a semiconductor device contacts a charged human body or a charged apparatus, static electricity charged in the human body or apparatus is discharged into an internal circuit of the semiconductor device through external pins via input/output pads so that a transient current with great energy flows into the internal circuit, thus causing severe damage to the semiconductor device. In addition, when a charged semiconductor device contacts an apparatus, the static electricity charged in the internal circuit of the semiconductor device may be discharged to the outside through the apparatus. This also may result in a transient current flowing into the internal circuit, which causes damage to the semiconductor device.
Accordingly, in most semiconductor integrated circuits, the ESD protection circuits are provided between the input/output pads and internal circuits of semiconductor devices in order to prevent the damage caused by the ESD.
FIG. 1 is a circuit diagram illustrating the ESD circuit that is provided to an output terminal of a source driver in a drive IC chip of a liquid crystal display.
Referring to FIG. 1, the typical ESD protection circuit has too small area to integrate clamp circuits that can withstand the electrostatic stress in each pad. Consequently, a current is generally discharged through diodes MPD and MND, as shown in FIG. 1. Most output voltages of a source driver have voltage levels between a ground voltage (i.e., 0 V) and a predetermined positive operating voltage. Accordingly, a circuit for driving the source driver is implemented with components having a positive operating voltage, and therefore the ESD protection circuit is also optimized to the operating voltage.
To be specific, the typical ESD protection circuit includes an input/output pad I/O, an output buffer 106, a transfer unit 108, and a clamp 110. The output buffer 106 transfers a source voltage to the input/output pad I/O. The transfer unit 108 transfers the static electricity inputted through the input/output pad I/O to various paths, thereby protecting internal circuits. The clamp 110 maintains a voltage difference between a power line 102 and a ground line 104 to a constant level. The typical ESD protection circuit further includes a switch unit 112 and a resistor 114 for transferring a signal transferred to the output buffer 106 to the input/output pad I/O.
The transfer unit 108 includes first and second diodes MPD and MND serially connected to each other in a forward direction. The first diode MPD is connected between the power line 102 and the input/output pad I/O. The second diode MND is connected between the input/output pad I/O and the ground line 104. A cathode terminal of the first diode MPD is connected to the power line 102, and an anode terminal of the first diode MPD is connected to the input/output pad I/O. A cathode terminal of the second diode MND is connected to the input/output pad I/O and an anode terminal of the second diode MND is connected to the ground line 104.
In a normal mode, the typical ESD protection circuit having the above-described configuration does not affect the circuit operation since both of the first and second diodes MPD and MND of the transfer unit 108 are reverse-biased and thus are turned off. However, when the static electricity is generated between the input/output pad I/O and a power supply voltage (VPP) pad or a ground voltage (VSS) pad, one of the first and second diodes MPD and MND operates to form an ESD path. As a result, the internal circuit can be prevented from being broken down by the static electricity flowing thereinto.
The above-described typical ESD protection circuit may be applied to a liquid crystal display having an operating voltage level ranging from a ground voltage level to a positive voltage level in a frame or line inversion scheme. However, unlike the frame or line inversion scheme, a liquid crystal display supporting a dot inversion scheme requires an operating voltage level ranging from a negative voltage level to a positive voltage level. That is, in the dot inversion scheme, the operating voltage should not only be in a ground-to-positive voltage range, but also in a negative-to-ground voltage range.
Thus, the typical ESD protection circuit of FIG. 1 cannot be applied to the liquid crystal display supporting a dot inversion scheme.